The present invention relates generally to integrated circuits. More particularly, the present invention relates to system-on-a-chip (SoC) test interface security.
Recent advances in integrated circuit technology have led to the proliferation of so-called system-on-a-chip (SoC) integrated circuits, where a processor is embedded with memory and other hardware blocks such as application-specific circuits on a single integrated circuit chip. FIG. 1 shows a prior art SoC 100 comprising a processor 102, a non-volatile memory 104, a volatile memory 106, a read-only memory (ROM) 108, a test interface 110, and application-specific circuit 112.
SoC 100 usually comprises a test interface 110, such as a Joint Test Action Group (JTAG) interface, for use in debugging and testing the SoC 100. Test interface 110 is generally connected to processor 102 and application-specific circuit 112, and can be connected to other circuits in SoC 100 as well. For example, test interface 100 can be used to trace the execution by processor 102 of firmware stored in non-volatile memory 104.
However, while useful during development, test interface 10 also provides a opening for attackers to penetrate SoC 100 once deployed in the field. For example, an attacker can use test interface 110 to copy or modify the firmware to break the security of systems in which SoC 100 is deployed. SoC 100 may employ secrets such as secret keys to prevent unauthorized access to certain resources. For example, a SoC 100 deployed in a Digital Video Disc (DVD) player/burner can employ a secret key to prevent a user from making copies of a copy-protected DVD. An attacker can use test interface 110 to obtain the secret key, and then use the DVD player/burner to make copies of copy-protected DVDs.